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Reduced stall MIPS architecture using pre-fetching accelerator
Zulkifli M.a, Yudhanto Y.P.a, Soetharyo N.A.a, Adiono T.a
a School of Electrical Engineering and Informatics, Institut Teknologi Bandung, Indonesia
[vc_row][vc_column][vc_row_inner][vc_column_inner][vc_separator css=”.vc_custom_1624529070653{padding-top: 30px !important;padding-bottom: 30px !important;}”][/vc_column_inner][/vc_row_inner][vc_row_inner layout=”boxed”][vc_column_inner width=”3/4″ css=”.vc_custom_1624695412187{border-right-width: 1px !important;border-right-color: #dddddd !important;border-right-style: solid !important;border-radius: 1px !important;}”][vc_empty_space][megatron_heading title=”Abstract” size=”size-sm” text_align=”text-left”][vc_column_text]This paper describes the design of a MIPS architecture with a small number of stall. Stall frequently happens in pipeline architecture which results in larger clock cycles. In this paper we significantly reduced stall by introducing pre-fetching unit. This unit reduces stall by concurrently reading three instructions and check their possibility of stall. If stall is detected, this unit then changes the sequence of executed instructions. Furthermore, we also employ forwarding and memory hazard detection units to further reduce stall. In order to increase the processor functionality and performances, especially for RSA security application, we include two new instructions 32-bit mult and mod. The design has been successfully implemented in FPGA DE2 Board (Terasic) and standard call CMOS 0.13u. As system verification, we successfully execute bubble sort program and RSA encryption. The system implementation reach the maximum frequency of 714 MHz. © 2009 IEEE.[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Author keywords” size=”size-sm” text_align=”text-left”][vc_column_text]Bubble sort,Clock cycles,Executed instructions,Hazard detection,Maximum frequency,MIPS architecture,Pipeline architecture,Pre-fetching accelerator,Prefetching,RSA encryption,RSA security,System implementation,System verifications[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Indexed keywords” size=”size-sm” text_align=”text-left”][vc_column_text]Pipeline,Pre-fetching accelerator,Prediction unit,RSA[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Funding details” size=”size-sm” text_align=”text-left”][vc_column_text][/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”DOI” size=”size-sm” text_align=”text-left”][vc_column_text]https://doi.org/10.1109/ICEEI.2009.5254742[/vc_column_text][/vc_column_inner][vc_column_inner width=”1/4″][vc_column_text]Widget Plumx[/vc_column_text][/vc_column_inner][/vc_row_inner][/vc_column][/vc_row][vc_row][vc_column][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][/vc_column][/vc_row]