DVB-T synchronizer architecture design and implementation
Adiono T.a, Cahyadi W.A.a, Salman A.H.a
a Electrical Engineering Department, School of Electrical Engineering and Informatics, Bandung Institute of Technology, Indonesia
Abstract
This paper presents the design of synchronizer hardware for DVB-T receiver. The main function of synchronizer is to detect and compensate the time offset and frequency offset which happen during transmission as well as frame start detection. Proposed synchronizer utilizes cyclic prefix of OFDM signals. The design includes computational bit precision modeling, architecture design, register-transfer-level (RTL) codes implementation, and final synthesis into FPGA. The synthesis result shows that the synchronizer can satisfy the required specification of at least more than 40MHz clock speed, i.e., specifically 55MHz clock setup. © 2009 IEEE.
Author keywords
Architecture designs,Clock speed,Cyclic Prefix,DVB-T,DVB-T receivers,Frequency offsets,OFDM signal,Register transfer level,Time offsets
Indexed keywords
Cyclic prefix,DVB-T,OFDM,Register-transfer-level,Synchronizer,WiMAX