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Very fast pipelined RSA architecture based on montgomery’s algorithm
Iput H.K.a, Asep B.N.a, Purba R.S.a, Adiono T.a
a Electrical Engineering Department, School of Electrical Engineering and Informatics, Bandung Institute of Technology, Indonesia
[vc_row][vc_column][vc_row_inner][vc_column_inner][vc_separator css=”.vc_custom_1624529070653{padding-top: 30px !important;padding-bottom: 30px !important;}”][/vc_column_inner][/vc_row_inner][vc_row_inner layout=”boxed”][vc_column_inner width=”3/4″ css=”.vc_custom_1624695412187{border-right-width: 1px !important;border-right-color: #dddddd !important;border-right-style: solid !important;border-radius: 1px !important;}”][vc_empty_space][megatron_heading title=”Abstract” size=”size-sm” text_align=”text-left”][vc_column_text]This paper present a design of RSAEncryption using Pipelined radix-2 Montgomery’s architecture. The architecture design exploits the algorithm to achieve high speed and efficient computation. The design separates the computation of Montgomery modular multiplication into different clock cycles to achieve high frequency clock. This design supports input from 1 to 14 block data and efficient in the number of total logic element and register. The design has been successfully verified whether functional Verilog RTL simulation, FPGA timing simulation and run in Signal Tap FPGA simulation. The design occupies logic elements 1157, 1030 registers, and able to run up to 261.85 MHz on Altera Cyclone II EP2C35 F672C6. The proposed design has been successfully synthesized using Synopsys with CMOS 0.18ì technology. The area is 63567.5 ìm2 and the delay is 3.35 ns. © 2009 IEEE.[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Author keywords” size=”size-sm” text_align=”text-left”][vc_column_text]Altera cyclones,Architecture designs,Clock cycles,Design support,Efficient computation,High frequency clocks,Logic elements,Montgomery,Montgomery modular multiplication,Montgomery’s Algorithm,Pipeline architecture,Radix 2,RSA architecture,Synopsys,Verilog[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Indexed keywords” size=”size-sm” text_align=”text-left”][vc_column_text]FPGA,Montgomery,Pipeline architecture,RSA[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Funding details” size=”size-sm” text_align=”text-left”][vc_column_text][/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”DOI” size=”size-sm” text_align=”text-left”][vc_column_text]https://doi.org/10.1109/ICEEI.2009.5254686[/vc_column_text][/vc_column_inner][vc_column_inner width=”1/4″][vc_column_text]Widget Plumx[/vc_column_text][/vc_column_inner][/vc_row_inner][/vc_column][/vc_row][vc_row][vc_column][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][/vc_column][/vc_row]