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Ultra-fast-scalable BCH decoder with efficient-Extended Fast Chien Search
Kristian H.a, Wahyono H.a, Rizki K.a, Adiono T.a
a Bandung Institute of Technology (ITB), School of Electrical and Informatics Engineering, Indonesia
[vc_row][vc_column][vc_row_inner][vc_column_inner][vc_separator css=”.vc_custom_1624529070653{padding-top: 30px !important;padding-bottom: 30px !important;}”][/vc_column_inner][/vc_row_inner][vc_row_inner layout=”boxed”][vc_column_inner width=”3/4″ css=”.vc_custom_1624695412187{border-right-width: 1px !important;border-right-color: #dddddd !important;border-right-style: solid !important;border-radius: 1px !important;}”][vc_empty_space][megatron_heading title=”Abstract” size=”size-sm” text_align=”text-left”][vc_column_text]In this paper, we introduced new methods in implementing ultra-fast-efficient BCH decoder that frequently used in many applications. A Reformulated inversionless-Berlekamp- Massey algorithm is adopted in order to eliminate the finite-field inverter and to reduce the hardware complexity. Furthermore, we proposed a Direct reformulated-inversionless Berlekamp-Massey algorithm (DriBM). While in the Chien Search stage, the Constant-Factor Multiplication-Free Matrix transform is also introduced to avoid expensiveness which significantly reduce the area and critical path. Moreover, we also developed Extended Fast Chien Search algorithm which significantly reduce computation complexity and the area by nearly 33% compared to Constant-Factor MFTM. Using our proposed design, we design a BCH(15,7) decoder which can reach speed up to 2.2 GHz with total area of is 8170μm2 using 0.18μm CMOS standard cell technology. The merits of the proposed algorithms and architecture are very efficient and fast. The implementation of the proposed BCH decoder architecture is also scalable to higher n block lengths and t number of correctable error, by using the same concept as we design BCH(63,51) using the same concept as BCH(15,7). In addition to the parallel BCH Decoder, we also design an area efficient parallel GF multiplier and squarer which minimized the number of logic gates. This design has been implemented and verified on Altera DE2 FPGA using codeword with various error positions and weight (0-2 guaranteed error correction). Due to its low complexity, it is suitable for VLSI implementation and also provide excellent tradeoffs between the correcting capacity, speed and area penalties. © 2010 IEEE.[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Author keywords” size=”size-sm” text_align=”text-left”][vc_column_text]Area efficient,Area penalty,BCH decoder,Berlekamp-Massey algorithm,Block lengths,Chien search,CMOS standard cell technology,Codeword,Computation complexity,Correcting capacity,Critical Paths,Decoder architecture,GF multiplier,Hardware complexity,Low complexity,Matrix transforms,Speed-ups,Ultra-fast,VLSI architectures,VLSI implementation[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Indexed keywords” size=”size-sm” text_align=”text-left”][vc_column_text]BCH decoder,Ultra-fast-scalable-efficient,VLSI architecture[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Funding details” size=”size-sm” text_align=”text-left”][vc_column_text][/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”DOI” size=”size-sm” text_align=”text-left”][vc_column_text]https://doi.org/10.1109/ICCSIT.2010.5564592[/vc_column_text][/vc_column_inner][vc_column_inner width=”1/4″][vc_column_text]Widget Plumx[/vc_column_text][/vc_column_inner][/vc_row_inner][/vc_column][/vc_row][vc_row][vc_column][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][/vc_column][/vc_row]