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A comparison of two VLSI architectures for integer discrete wavelet transforms
a ITB Research Center on Information and Communication Technology, Indonesia
b DSP-RTG, Information Technology Research Division, School of Electrical Engineering and Informatics, Indonesia
c ITB MicrolectronicCenter, InstitutTeknologi Bandung, Indonesia
[vc_row][vc_column][vc_row_inner][vc_column_inner][vc_separator css=”.vc_custom_1624529070653{padding-top: 30px !important;padding-bottom: 30px !important;}”][/vc_column_inner][/vc_row_inner][vc_row_inner layout=”boxed”][vc_column_inner width=”3/4″ css=”.vc_custom_1624695412187{border-right-width: 1px !important;border-right-color: #dddddd !important;border-right-style: solid !important;border-radius: 1px !important;}”][vc_empty_space][megatron_heading title=”Abstract” size=”size-sm” text_align=”text-left”][vc_column_text]This paper compares two different VLSI architectures for discrete wavelet transform (DWT) in terms of finite word-length effects and architecture complexity. We consider two DWT architectures representing two extreme cases: (i) Scheme 1: basis correlation, and (ii) Scheme 2: pyramidal algorithm. The performance of the schemes is evaluated according to: (i) the length of input vector (N), (ii) the length of wavelet prototype (L), and (iii) the length of integer word (W). Our experiments to assess round-off effects show that W is critical for both schemes, although both schemes perform almost equivalently. Other experiments also show that N and L have no significant effects on the SNR. In terms of complexity, Scheme 2 requires fewer computational operations (i.e., multiplication and addition), but Scheme 1 has simpler structures. This paper shows that Scheme 2 has multiplication complexity O(N), while Scheme 1 has O(N2). Thus for a typical N and L of 64 and 4, respectively, Schemes 1 and 2 result in 3900 and 512 operations, respectively. © 2011 IEEE.[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Author keywords” size=”size-sm” text_align=”text-left”][vc_column_text]Computational operations,DWT,Input vector,Multiplication complexity,Pyramidal Algorithm,VLSI architectures,Word length[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Indexed keywords” size=”size-sm” text_align=”text-left”][vc_column_text]DWT,Pyramidal Algorithm,VLSI Architecture[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Funding details” size=”size-sm” text_align=”text-left”][vc_column_text][/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”DOI” size=”size-sm” text_align=”text-left”][vc_column_text]https://doi.org/10.1109/ICEEI.2011.6021670[/vc_column_text][/vc_column_inner][vc_column_inner width=”1/4″][vc_column_text]Widget Plumx[/vc_column_text][/vc_column_inner][/vc_row_inner][/vc_column][/vc_row][vc_row][vc_column][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][/vc_column][/vc_row]