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An FPGA implementation of a simple lossless data compression coprocessor
a ITB Research Center on Information and Communication Technology, Indonesia
b DSP-RTG, Information Technology Research Division, School of Electrical Engineering and Informatics, Indonesia
c ITB MicrolectronicCenter, InstitutTeknologi Bandung, Indonesia
[vc_row][vc_column][vc_row_inner][vc_column_inner][vc_separator css=”.vc_custom_1624529070653{padding-top: 30px !important;padding-bottom: 30px !important;}”][/vc_column_inner][/vc_row_inner][vc_row_inner layout=”boxed”][vc_column_inner width=”3/4″ css=”.vc_custom_1624695412187{border-right-width: 1px !important;border-right-color: #dddddd !important;border-right-style: solid !important;border-radius: 1px !important;}”][vc_empty_space][megatron_heading title=”Abstract” size=”size-sm” text_align=”text-left”][vc_column_text]The paper describes a Field Programmable Gate Array (FPGA)-based lossless data compression coprocessor using implementing a compression method developed by Rice. We have implemented the Rice code (both encoder and decoder) for 8 bit/sample data on an FPGA Xilinx XC4005. The code has been designed to be optimal on 1.5 < H < 7.5 bits/sample, that is usually required in lossless image compression. The encoder and decoder can achieve 11.6 MHz and 19.4 MHz clock, respectively, where a 10 MHz clock corresponds to a 1.5 Mbits/s throughput. The XC4005 contains combinatorial logic units (CLU) and I/O pins. The Rice encoder uses 30% CLB F&G, 15% CLB H, 16% CLB FF, and 34% I/O pins. The Rice decoder uses 31% CLB F&G, 19% CLB H, 16% CLB FF, and 34% I/O pin. Hence, an X4005 is sufficient to implement both encoder and decoder. © 2011 IEEE.[/vc_column_text][vc_empty_space][vc_separator css=".vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}"][vc_empty_space][megatron_heading title="Author keywords" size="size-sm" text_align="text-left"][vc_column_text]Co-processors,Combinatorial logic,Compression methods,FPGA implementations,I/O pins,Lossless compression,Lossless data compression,Lossless image compression,Rice coder[/vc_column_text][vc_empty_space][vc_separator css=".vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}"][vc_empty_space][megatron_heading title="Indexed keywords" size="size-sm" text_align="text-left"][vc_column_text]FPGA Implementation,Lossless Compression,Rice coder[/vc_column_text][vc_empty_space][vc_separator css=".vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}"][vc_empty_space][megatron_heading title="Funding details" size="size-sm" text_align="text-left"][vc_column_text][/vc_column_text][vc_empty_space][vc_separator css=".vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}"][vc_empty_space][megatron_heading title="DOI" size="size-sm" text_align="text-left"][vc_column_text]https://doi.org/10.1109/ICEEI.2011.6021669[/vc_column_text][/vc_column_inner][vc_column_inner width=”1/4″][vc_column_text]Widget Plumx[/vc_column_text][/vc_column_inner][/vc_row_inner][/vc_column][/vc_row][vc_row][vc_column][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][/vc_column][/vc_row]