This paper describes a hardware architectural design of a real-time counter based entropy coder at a register transfer level (RTL) computing model. The architecture is based on a lossless compression algorithm called Rice coding, which is optimal for an entropy range of 1.5 < H < 2.5 bits per sample. The architecture incorporates a word-splitting scheme to extend the entropy coverage into a range of 1.5 < H < 7.5 bits per sample. We have designed a data structure in a form of independent code blocks, allowing more robust compressed bitstream. The design focuses on an RTL computing model and architecture, utilizing 8-bit buffers, adders, registers, loader-shifters, select-logics, down-counters, up-counters, and multiplexers. We have validated the architecture (both the encoder and the decoder) in a coprocessor for 8 bits/sample data on an FPGA Xilinx XC4005, utilizing 61% of F&G-CLBs, 34% H-CLBs, 32% FF-CLBs, and 68% IO resources. On this FPGA implementation, the encoder and decoder can achieve 1.74 Mbits/s and 2.91 Mbits/s throughputs, respectively. The architecture allows pipelining, resulting in potentially maximum encoding throughput of 200 Mbit/s on typical real-time TTL implementations. In addition, it uses a minimum number of register elements. As a result, this architecture can result in low cost, low energy consumption and reduced silicon area realizations. © 2012 Published by LPPM ITB & PII.

Bit stream,Co-processors,Code blocks,Computing model,Counter-based coder,Encoding throughput,Entropy coders,FPGA implementations,Hardware architecture,Lossless compression,Lossless compression algorithm,Low costs,Low energy consumption,Register transfer level,Rice coding,RTL,Silicon area

Counter-based coder,Hardware architecture,Lossless compression,RTL

https://doi.org/10.5614/itbj.eng.sci.2012.44.1.3