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SOC design and FPGA implementation of Digital TV receiver
Salman A.H.a, Adiono T.a, Cahyadi W.A.a, Kurniawan Y.a
a Electrical Engineering, School of Electrical Engineering and Informatics, Institut Teknologi Bandung, Indonesia
[vc_row][vc_column][vc_row_inner][vc_column_inner][vc_separator css=”.vc_custom_1624529070653{padding-top: 30px !important;padding-bottom: 30px !important;}”][/vc_column_inner][/vc_row_inner][vc_row_inner layout=”boxed”][vc_column_inner width=”3/4″ css=”.vc_custom_1624695412187{border-right-width: 1px !important;border-right-color: #dddddd !important;border-right-style: solid !important;border-radius: 1px !important;}”][vc_empty_space][megatron_heading title=”Abstract” size=”size-sm” text_align=”text-left”][vc_column_text]This paper proposes a System-on-chip (SoC) Architecture Design for real-time Digital TV receiver. The SoC includes RF interface, a Host Processor, a Physical Layer and Ethernet interface. The Physical Layer itself consists of Baseband Processing modules based on DVB-T standard which includes 2048-point FFT/IFFT, Channel Decoder, Synchronizer, Equalizer, Demodulator, etc. The SoC utilizes a 32-bit RISC based processor acting as the Host Processor. Both Processor and Physical layer works on 32 MHz clock cycle to ensure low power consumption. A real-time OS based on eCos is also used for controlling the Physical Layer and interfaces in a real-time basis. The system is implemented using FPGA and has been verified capable of receiving a realtime video transmitted by a standard digital TV transmitter/modulator. © 2012 IEEE.[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Author keywords” size=”size-sm” text_align=”text-left”][vc_column_text]DVB-T,eCos,MPEG,Platform,SoC[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Indexed keywords” size=”size-sm” text_align=”text-left”][vc_column_text]DVB-T,eCos,Integration,MPEG,Platform,RISC,SoC[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Funding details” size=”size-sm” text_align=”text-left”][vc_column_text][/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”DOI” size=”size-sm” text_align=”text-left”][vc_column_text]https://doi.org/10.1109/TSSA.2012.6366036[/vc_column_text][/vc_column_inner][vc_column_inner width=”1/4″][vc_column_text]Widget Plumx[/vc_column_text][/vc_column_inner][/vc_row_inner][/vc_column][/vc_row][vc_row][vc_column][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][/vc_column][/vc_row]