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Efficient equalization hardware architecture for SC-FDMA systems without cyclic prefix
Ferdian R.a, Anwar K.b, Adiono T.a
a School of Electrical Engineering and Informatics, Institut Teknologi Bandung (ITB), Indonesia
b School of Information Science, Japan Advanced Institute of Science and Technology (JAIST), Japan
[vc_row][vc_column][vc_row_inner][vc_column_inner][vc_separator css=”.vc_custom_1624529070653{padding-top: 30px !important;padding-bottom: 30px !important;}”][/vc_column_inner][/vc_row_inner][vc_row_inner layout=”boxed”][vc_column_inner width=”3/4″ css=”.vc_custom_1624695412187{border-right-width: 1px !important;border-right-color: #dddddd !important;border-right-style: solid !important;border-radius: 1px !important;}”][vc_empty_space][megatron_heading title=”Abstract” size=”size-sm” text_align=”text-left”][vc_column_text]Single carrier frequency domain multiple access (SC-FDMA) system achieves better spectral efficiency when cyclic prefix (CP) is not transmitted. However, the chained turbo equalization (CHATUE) algorithm, an equalizer required to both equalize the multipath fading effect and cancel the inter-block interference of SC-FDMA without CP, requires high computational complexity due to the non-circulant structure of the past and the future interference matrices. This paper proposes efficient hardware architecture based on systolic architecture for practical implementation. The main idea is to minimize the number of required processing elements by utilizing efficient resources sharing method while exploiting concurrency of the processing. A new computation method using masking matrices is introduced to obtain interference matrix from its corresponding circulant channel matrix. The results with fixed point computation show that the computational complexity can be significantly reduced up to 96% for practical implementation without significant degradation in bit-error-rate (BER) performances. © 2012 IEEE.[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Author keywords” size=”size-sm” text_align=”text-left”][vc_column_text]Channel matrices,Circulants,Computation methods,Cyclic Prefix,Fixed-point computation,Hardware architecture,Interblock interference,Interference matrix,Multipath fading effects,Multiple access,Practical implementation,Processing elements,Resources sharing,SC-FDMA,Single carrier,Spectral efficiencies,Systolic architecture,Turbo equalizations[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Indexed keywords” size=”size-sm” text_align=”text-left”][vc_column_text][/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Funding details” size=”size-sm” text_align=”text-left”][vc_column_text][/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”DOI” size=”size-sm” text_align=”text-left”][vc_column_text]https://doi.org/10.1109/ISCIT.2012.6381038[/vc_column_text][/vc_column_inner][vc_column_inner width=”1/4″][vc_column_text]Widget Plumx[/vc_column_text][/vc_column_inner][/vc_row_inner][/vc_column][/vc_row][vc_row][vc_column][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][/vc_column][/vc_row]