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New macroblock engine architecture for video processing
Adiono T.a, Fitriyanto D.a, Mulyanto A.a, Wisayataksin S.b, Takeichi K.b, Li D.b, Mengko T.R.a, Kunieda H.b
a Department of Electrical Engineering, Bandung Institute of Technology, Indonesia
b Department of Communications and Integrated Systems, Tokyo Institute of Technology, Japan
[vc_row][vc_column][vc_row_inner][vc_column_inner][vc_separator css=”.vc_custom_1624529070653{padding-top: 30px !important;padding-bottom: 30px !important;}”][/vc_column_inner][/vc_row_inner][vc_row_inner layout=”boxed”][vc_column_inner width=”3/4″ css=”.vc_custom_1624695412187{border-right-width: 1px !important;border-right-color: #dddddd !important;border-right-style: solid !important;border-radius: 1px !important;}”][vc_empty_space][megatron_heading title=”Abstract” size=”size-sm” text_align=”text-left”][vc_column_text]A new engine for macro-block based video processing is introduced in this paper. This engine increases efficiency, flexibility and extensibility of data generation for macroblock based video processing system. In the proposed system, a new specific instruction sets that can access data in pixel, line, block, macro-block or frame within a clock cycle are introduced. Thus, efficiency of video processing system is increased. Additionally, the programmability of data access enables dynamic scheduling for various video processing applications. It extremely reduces processing time while reducing the control complexity as well. This architecture also has scalability for different size of image and has expandability for new macro-block based processor. Implementation to typical video compression application shows high performance result and easy system implementation. Copyright © 2005 by MVA Conference Committee.[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Author keywords” size=”size-sm” text_align=”text-left”][vc_column_text]Clock cycles,Control complexity,Data access,Data generation,Different sizes,Dynamic scheduling,Expandability,Macro block,Processing time,Programmability,Specific instruction,System implementation,Video processing,Video processing applications[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Indexed keywords” size=”size-sm” text_align=”text-left”][vc_column_text][/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Funding details” size=”size-sm” text_align=”text-left”][vc_column_text][/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”DOI” size=”size-sm” text_align=”text-left”][vc_column_text][/vc_column_text][/vc_column_inner][vc_column_inner width=”1/4″][vc_column_text]Widget Plumx[/vc_column_text][/vc_column_inner][/vc_row_inner][/vc_column][/vc_row][vc_row][vc_column][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][/vc_column][/vc_row]