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FPGA implementation of fast serial 64-points FFT/IFFT block without reordering block
Kasim M.F.a, Adiono T.a, Fahreza M.a, Zakiy M.F.a
a Sekolah Teknik Elektro Informatika, Institut Teknologi Bandung, Indonesia
[vc_row][vc_column][vc_row_inner][vc_column_inner][vc_separator css=”.vc_custom_1624529070653{padding-top: 30px !important;padding-bottom: 30px !important;}”][/vc_column_inner][/vc_row_inner][vc_row_inner layout=”boxed”][vc_column_inner width=”3/4″ css=”.vc_custom_1624695412187{border-right-width: 1px !important;border-right-color: #dddddd !important;border-right-style: solid !important;border-radius: 1px !important;}”][vc_empty_space][megatron_heading title=”Abstract” size=”size-sm” text_align=”text-left”][vc_column_text]There has been many FPGA implementation of serial Fast Fourier Transform (FFT) operation. In the most cases, output of the serial FFT block is in bit-reversed order, so it needs a reordering block to reorder the output. However, some of FFT applications do not require ordered output of FFT, such like Spectral Subtraction method[1]. In this paper, we propose an FPGA implementation of serial FFT and IFFT architecture in one block without reordering block. By not implementing the reordering block, we can save some clock cycles latency and increase speed of the block. The architecture is implemented in Altera DE2-70 board with Cyclone II EP2C35F672C6 FPGA chip. Our 64-points FFT/IFFT block utilizes 2960 logic elements or half of logic elements utilized by Altera MegaFunction’s FFT IP. The block can work in maximum frequency of 84.55MHz and perform 64-points FFT/IFFT operation in 863.4ns. © 2013 IEEE.[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Author keywords” size=”size-sm” text_align=”text-left”][vc_column_text]Clock cycles,FFT/IFFT,FPGA chips,FPGA implementations,Logic elements,Maximum frequency,reordering block,Spectral subtraction methods[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Indexed keywords” size=”size-sm” text_align=”text-left”][vc_column_text]FFT,FPGA implementation,reordering block[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Funding details” size=”size-sm” text_align=”text-left”][vc_column_text][/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”DOI” size=”size-sm” text_align=”text-left”][vc_column_text]https://doi.org/10.1109/ICIEV.2013.6572558[/vc_column_text][/vc_column_inner][vc_column_inner width=”1/4″][vc_column_text]Widget Plumx[/vc_column_text][/vc_column_inner][/vc_row_inner][/vc_column][/vc_row][vc_row][vc_column][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][/vc_column][/vc_row]