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VHDL design and simulation of MAM memory for LAPCAM parallel architecture for image processing
Darmawan I.a, Hartono W.T.b, Mozef E.b, Sutikno S.c, Kuspriyantoc
a Department of Electrical Engineering, University of Siliwangi, Tasikmalaya, Indonesia
b Department of Electrical Engineering, Politeknik Negeri Bandung, Bandung, Indonesia
c Department of Electrical Engineering, Institut Teknologi Bandung, Bandung, Indonesia
[vc_row][vc_column][vc_row_inner][vc_column_inner][vc_separator css=”.vc_custom_1624529070653{padding-top: 30px !important;padding-bottom: 30px !important;}”][/vc_column_inner][/vc_row_inner][vc_row_inner layout=”boxed”][vc_column_inner width=”3/4″ css=”.vc_custom_1624695412187{border-right-width: 1px !important;border-right-color: #dddddd !important;border-right-style: solid !important;border-radius: 1px !important;}”][vc_empty_space][megatron_heading title=”Abstract” size=”size-sm” text_align=”text-left”][vc_column_text]© 2002 IEEE.MAM (multi-mode access memory) is a memory that has the characteristics of PSMU (parallel search and multiple update). This new type of memory is applied to LAPCAM (linear array of processors with content addressable memory) architecture for image processing. Using MAM, the global and regional type of image processing algorithms can be developed efficiently. MAM consists of 3 different types of memory i.e. conventional memory (RAM), content addressable memory (CAM), and shift/rotate memory (FIFO). The objectives of the research are focused on the design of MAM memory, implementation of the design in VHDL (VHSIC hardware description language), verification of the design by simulation using software active-HDL and evaluation of the simulation results.[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Author keywords” size=”size-sm” text_align=”text-left”][vc_column_text]Associative memory,CADCAM,Hardware design language,Random access memory,Very high speed integrated circuits[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Indexed keywords” size=”size-sm” text_align=”text-left”][vc_column_text]Associative memory,CADCAM,Computer aided manufacturing,Hardware design languages,Image processing,Memory architecture,Parallel architectures,Random access memory,Read-write memory,Very high speed integrated circuits[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Funding details” size=”size-sm” text_align=”text-left”][vc_column_text][/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”DOI” size=”size-sm” text_align=”text-left”][vc_column_text]https://doi.org/10.1109/APCCAS.2002.1114976[/vc_column_text][/vc_column_inner][vc_column_inner width=”1/4″][vc_column_text]Widget Plumx[/vc_column_text][/vc_column_inner][/vc_row_inner][/vc_column][/vc_row][vc_row][vc_column][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][/vc_column][/vc_row]