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FPGA implementation of CORDIC algorithms for sine and cosine generator
Renardy A.P.a, Ahmadi N.a, Fadila A.A.a, Shidqi N.a, Adiono T.a
a Department of Electrical Engineering, School of Electrical Engineering and Informatics, Bandung Institute of Technology, Bandung, 40132, Indonesia
[vc_row][vc_column][vc_row_inner][vc_column_inner][vc_separator css=”.vc_custom_1624529070653{padding-top: 30px !important;padding-bottom: 30px !important;}”][/vc_column_inner][/vc_row_inner][vc_row_inner layout=”boxed”][vc_column_inner width=”3/4″ css=”.vc_custom_1624695412187{border-right-width: 1px !important;border-right-color: #dddddd !important;border-right-style: solid !important;border-radius: 1px !important;}”][vc_empty_space][megatron_heading title=”Abstract” size=”size-sm” text_align=”text-left”][vc_column_text]© 2015 IEEE.Trigonometric-related calculations which are widely found in a broad range of applications can be performed by using COordinate Rotation DIgital Computer (CORDIC) algorithm. CORDIC is often utilized in the absence of hardware multiplier since this algorithm requires only addition, subtraction, bit shifting, and lookup table. This paper provides an implementation of conventional CORDIC algorithm with pipelined architecture and Virtually Scaling-Free Adaptive (VSFA) CORDIC. All designs are implemented in Verilog and synthesized by using Altera Quartus II with FPGA DE2 as target board. The pipelined CORDIC consumes 1,103 logic element, 33.32 ns latency, and 420.17 MHz maximum frequency, while VSFA CORDIC utilizes 2,109 logic element, 34.96 ns latency, and 343.29 MHz maximum frequency. Both designs are used to generate sine and cosine wave between -π and π which result in maximum error of 8.095 ×2-13 for pipelined CORDIC and 9.183 × 2-13 for VSFA CORDIC. Based on performance comparison in term of area multiplied by delay (A × T), our pipelined CORDIC is superior among other designs.[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Author keywords” size=”size-sm” text_align=”text-left”][vc_column_text]Coordinate rotation digital computer algorithms,CORDIC,FPGA implementations,Maximum frequency,Performance comparison,Pipelined architecture,Sine and Cosine Generator,VSFA[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Indexed keywords” size=”size-sm” text_align=”text-left”][vc_column_text]CORDIC,FPGA,Sine and Cosine Generator,VSFA[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Funding details” size=”size-sm” text_align=”text-left”][vc_column_text][/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”DOI” size=”size-sm” text_align=”text-left”][vc_column_text]https://doi.org/10.1109/ICEEI.2015.7352460[/vc_column_text][/vc_column_inner][vc_column_inner width=”1/4″][vc_column_text]Widget Plumx[/vc_column_text][/vc_column_inner][/vc_row_inner][/vc_column][/vc_row][vc_row][vc_column][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][/vc_column][/vc_row]