[vc_empty_space][vc_empty_space]
Small and compact Diversity Combining using selective method for mobile application
Sudirja A.F.D.A.a, Adiono T.a
a Electrical Engineering Dept., STEI ITB, Bandung, Indonesia
[vc_row][vc_column][vc_row_inner][vc_column_inner][vc_separator css=”.vc_custom_1624529070653{padding-top: 30px !important;padding-bottom: 30px !important;}”][/vc_column_inner][/vc_row_inner][vc_row_inner layout=”boxed”][vc_column_inner width=”3/4″ css=”.vc_custom_1624695412187{border-right-width: 1px !important;border-right-color: #dddddd !important;border-right-style: solid !important;border-radius: 1px !important;}”][vc_empty_space][megatron_heading title=”Abstract” size=”size-sm” text_align=”text-left”][vc_column_text]© 2015 IEEE.The destruction caused by channel can be seen by the existence of Amplitude and Phase Shift. By using the Diversity Combining method, It is expected that the disruption caused by Amplitude and Phase Shift can be suppressed as small as possible. In addition, by using Diversity Combining module, the signal will have a larger SNR output which has a value sum of SNR from each diversity path. The design of Diversity Combining module begins with MATLAB functional design as a big picture of the whole system. Subsequently, it will be made the hardware based on the MATLAB functional. This architectural design will be the cornerstone in the design of MATLAB bit precision (hardware precision). The hardware modelling using MATLAB bit precision will be designed as the foundation of the VHDL (hardware) design. In the end, the output shown that this paper results meet the standards specified by the DVB consortium. In the hardware (FPGA) test results of Diversity Combining, the maximum working frequency is 44.56 MHz which has shown that is qualified with the standard sampling clock (9.142 MHz). This design also needs 4% of total FPGA Cyclone II 484I8 combinational units which is 2499 units and it needs also 3% of total register of FPGA Cyclone II 484I8 which is 1720 register units.[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Author keywords” size=”size-sm” text_align=”text-left”][vc_column_text]Bit precision,Diversity combining,Functional design,Mobile applications,Sampling clocks,Selective combining,Working frequency[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Indexed keywords” size=”size-sm” text_align=”text-left”][vc_column_text]Diversity Combining,FPGA,Selective Combining[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Funding details” size=”size-sm” text_align=”text-left”][vc_column_text][/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”DOI” size=”size-sm” text_align=”text-left”][vc_column_text]https://doi.org/10.1109/ISPACS.2015.7432771[/vc_column_text][/vc_column_inner][vc_column_inner width=”1/4″][vc_column_text]Widget Plumx[/vc_column_text][/vc_column_inner][/vc_row_inner][/vc_column][/vc_row][vc_row][vc_column][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][/vc_column][/vc_row]