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Hybrid multi System-on-Chip architecture: A rapid development design for high-flexibility system
Putra R.V.W.a, Adiono T.a
a Microelectronics Center, Institut Teknologi Bandung, Indonesia
[vc_row][vc_column][vc_row_inner][vc_column_inner][vc_separator css=”.vc_custom_1624529070653{padding-top: 30px !important;padding-bottom: 30px !important;}”][/vc_column_inner][/vc_row_inner][vc_row_inner layout=”boxed”][vc_column_inner width=”3/4″ css=”.vc_custom_1624695412187{border-right-width: 1px !important;border-right-color: #dddddd !important;border-right-style: solid !important;border-radius: 1px !important;}”][vc_empty_space][megatron_heading title=”Abstract” size=”size-sm” text_align=”text-left”][vc_column_text]© 2016 IEEE.In this paper, we propose a System-on-Chip (SoC) architecture that provides a high-flexibility system in a rapid development time. It is called Hybrid Multi SoC (H-MSoC). H-MSoC provides flexible SoC architecture that is easy to configure for physical and application layers development. These two aspects (physical and application layers) are dynamically designed and modified, hence it is important to consider and optimize their design methodology to support rapid SoC development. Physical layer development refers to Intellectual Property (IP) cores or hardware developments, while application layer development refers to user and interface application developments. H-MSoC is established from multi-SoC architectures which each SoC is localized and specified based on its development layer, either physical or application (hybrid). Physical layer development SoC is called Physical-SoC (Phy-SoC) and application layer development SoC is called Application-SoC (App-SoC). Phy-SoC and App-SoC are connected to each other via ethernet. Ethernet is chosen because of its flexibility, high-speed, and easiness for configuration. For prototyping purpose, we used LEON3 SoC as Phy-SoC and ZYNQ-7000 SoC as App-SoC. Proposed design has been proved in real time testing and achieved good performance.[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Author keywords” size=”size-sm” text_align=”text-left”][vc_column_text]Development designs,H-MSoC,Hardware development,High flexibility,Intellectual property cores,Interface applications,rapid development,System-on-chip architecture[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Indexed keywords” size=”size-sm” text_align=”text-left”][vc_column_text]Application-SoC,H-MSoC,high-flexibility system,Physical-SoC,rapid development[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Funding details” size=”size-sm” text_align=”text-left”][vc_column_text][/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”DOI” size=”size-sm” text_align=”text-left”][vc_column_text]https://doi.org/10.1109/ELINFOCOM.2016.7562962[/vc_column_text][/vc_column_inner][vc_column_inner width=”1/4″][vc_column_text]Widget Plumx[/vc_column_text][/vc_column_inner][/vc_row_inner][/vc_column][/vc_row][vc_row][vc_column][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][/vc_column][/vc_row]