An architecture design of SAD based template matching for fast queue counter in FPGA
Adiono T.a, Adhinata M.D.a, Prihatiningrum N.a, Disastra R.a, Putra R.V.W.a, Salman A.H.a
a Department of Electrical Engineering, School of Electrical Engineering and Informatics, Institut Teknologi Bandung, 40132, Indonesia
Abstract
© 2016 IEEE.In this paper, we propose an architecture design of Sum of Absolute Difference (SAD) based template matching for fast queue counter. The main idea of this architecture design are line delay and SAD processor array. Size of the line delay is 640×100, since the length of the source image is 640 pixels, the width of the template image is 100 pixels and specification of the template and source images are 640×480 and 40×100 pixels respectively. The processor array (PA) contains 40×100 SAD processing elements (PEs) that are mapped into horizontal structure. We synthesize and implement the proposed design in FPGA Altera DE2-115. It can reach 128.35 MHz as maximum frequency and occupies 59,899 memory bits; 17,158 registers and 17,411 combinationals. It needs 307,200 clock cycles to finish a single image. By using 100 MHz clock frequency, a single image processing can be conducted in 3.072 ms (325 fps). These results show that the proposed design can reach fast computational performance.
Author keywords
Architecture designs,Computational performance,Fast Queue Counter,Maximum frequency,Processing elements,Processor array,Sum of absolute differences,Template images
Indexed keywords
Fast Queue Counter,FPGA,Sum of Absolute Difference,Template Matching