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Full custom design of adaptable montgomery modular multiplier for asymmetric RSA cryptosystem
Adiono T.a, Ega H.a, Kasan H.a, Fuada S.a, Harimurti S.a
a University Center of Excellence on Microelectronics, Institut Teknologi Bandung, Bandung, 40132, Indonesia
[vc_row][vc_column][vc_row_inner][vc_column_inner][vc_separator css=”.vc_custom_1624529070653{padding-top: 30px !important;padding-bottom: 30px !important;}”][/vc_column_inner][/vc_row_inner][vc_row_inner layout=”boxed”][vc_column_inner width=”3/4″ css=”.vc_custom_1624695412187{border-right-width: 1px !important;border-right-color: #dddddd !important;border-right-style: solid !important;border-radius: 1px !important;}”][vc_empty_space][megatron_heading title=”Abstract” size=”size-sm” text_align=”text-left”][vc_column_text]© 2017 IEEE.The asymmetric RSA cryptosystem requires modulo operations in its encryption and decryption process, which is often realized with Montgomery modular multiplication. In this paper, we proposed a Montgomery multiplier hardware design using only primitive gates, adders, shifters, multiplexers, and registers. Our algorithm is also adaptable, which means that it can be reconfigured for applications with any arbitrary bits. The algorithm involves iteration, and to achieve less transistor count, we realized the iteration by feeding back the calculation results at the output back to the input, instead of connecting the gates in series. These considerations are made to allow us to create a compact custom ASIC design. The design was made with 130nm standard CMOS technology with NMOS and PMOS base width of 0.5jm and 1 urn respectively. With the algorithm, our 8-bit multiplier ASIC design occupies an area of 0.0266mm2. The design is created and verified with Mentor Graphics™ EDA tools.[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Author keywords” size=”size-sm” text_align=”text-left”][vc_column_text]adaptable,Calculation results,Encryption and decryption,iteration,Montgomery modular multiplication,Montgomery modular multiplier,Montgomery multipliers,Standard CMOS technology[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Indexed keywords” size=”size-sm” text_align=”text-left”][vc_column_text]adaptable,ASIC,iteration,Montgomery modular multiplication[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Funding details” size=”size-sm” text_align=”text-left”][vc_column_text][/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”DOI” size=”size-sm” text_align=”text-left”][vc_column_text]https://doi.org/10.1109/ISPACS.2017.8266605[/vc_column_text][/vc_column_inner][vc_column_inner width=”1/4″][vc_column_text]Widget Plumx[/vc_column_text][/vc_column_inner][/vc_row_inner][/vc_column][/vc_row][vc_row][vc_column][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][/vc_column][/vc_row]