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Design and simulation of hafnium dioxide based charge trapping flash memory device
Adiono T.a, Harimurti S.a, Meliolla G.a
a School of Electrical Engineering and Informatics, Institut Teknologi Bandung, Bandung, Indonesia
[vc_row][vc_column][vc_row_inner][vc_column_inner][vc_separator css=”.vc_custom_1624529070653{padding-top: 30px !important;padding-bottom: 30px !important;}”][/vc_column_inner][/vc_row_inner][vc_row_inner layout=”boxed”][vc_column_inner width=”3/4″ css=”.vc_custom_1624695412187{border-right-width: 1px !important;border-right-color: #dddddd !important;border-right-style: solid !important;border-radius: 1px !important;}”][vc_empty_space][megatron_heading title=”Abstract” size=”size-sm” text_align=”text-left”][vc_column_text]© 2017 IEEE.The demand of lower power and smaller dimension of flash memory requires size down scaling of the device. To meet this requirements, charge trapping flash using high-k dielectric is considered as one of the future technologies. In this paper, the design and simulation of HfO2 based charge trapping flash (CTF) is investigated. The CTF is based on a typical 160 nm NMOS structure with hafnium dioxide layer and ONO embedded in the gate stack. The program and erase (P/E) states of the device are simulated for several cycles to achieve stead-state charge density in trapping layer. Current-voltage characteristics are also run to extract threshold voltages of the P/E states. The threshold voltage shift is 0.82 V. A 10-year simulation is also taken to characterize the long-term charge retention capabilities of the structure. The device shows improved barrier tunnelling current and high retention ability for electron as well as their high density.[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Author keywords” size=”size-sm” text_align=”text-left”][vc_column_text]Charge-trapping flashes,Design and simulation,Double gate,Future technologies,High- k,Program and erase,Threshold voltage shifts,Tunnelling current[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Indexed keywords” size=”size-sm” text_align=”text-left”][vc_column_text]charge trapping,double gate,flash memory,high-k[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Funding details” size=”size-sm” text_align=”text-left”][vc_column_text][/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”DOI” size=”size-sm” text_align=”text-left”][vc_column_text]https://doi.org/10.1109/ICEEI.2017.8312447[/vc_column_text][/vc_column_inner][vc_column_inner width=”1/4″][vc_column_text]Widget Plumx[/vc_column_text][/vc_column_inner][/vc_row_inner][/vc_column][/vc_row][vc_row][vc_column][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][/vc_column][/vc_row]