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Study on first generation super flash memory cell fabrication using liftoff-techniques and its performance in floating gate and gate oxide thickness scaling
Sulthoni M.A.a, Sahbani B.a, Shiddieqy H.A.a, Siregar L.a
a School of Electrical Engineering and Informatics, Bandung Institute of Technology, Bandung, Indonesia
[vc_row][vc_column][vc_row_inner][vc_column_inner][vc_separator css=”.vc_custom_1624529070653{padding-top: 30px !important;padding-bottom: 30px !important;}”][/vc_column_inner][/vc_row_inner][vc_row_inner layout=”boxed”][vc_column_inner width=”3/4″ css=”.vc_custom_1624695412187{border-right-width: 1px !important;border-right-color: #dddddd !important;border-right-style: solid !important;border-radius: 1px !important;}”][vc_empty_space][megatron_heading title=”Abstract” size=”size-sm” text_align=”text-left”][vc_column_text]© 2017 IEEE.According to ITRS 2015, the CMOS-scaling is still potentially implemented in memory device technology. Therefore comprehensive studies should be done to investigate the correlation between certain physical parameter (gate oxide and floating gate thickness) and the device performance (power utilization and program-erase speed). In the SuperFlash Memory Cell, reliability of memory cell could be increased by the beak-like structure in the floating gate. In order to increase both device reliability and performance, this paper propose an improvement in fabrication process using lift-off techniques, and its analysis for floating gate amd gate oxide thickness scaling. By using several techniques in software based simulation software Synopsys ® Sentaurus, this paper points some conclusion that the proposed fabrication process is resulting clearer beak-like structure than the previous process. In the performance analysis, the floating gate thickness scaling could affect both the increasing of erased-programmed speed in flash memory and power utilization reduction.[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Author keywords” size=”size-sm” text_align=”text-left”][vc_column_text]Flash memory cell,Floating gates,Gate oxide thickness,Liftoff technique,Speed analysis[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Indexed keywords” size=”size-sm” text_align=”text-left”][vc_column_text]First Generation Super-Flash Memory Cell,Floating gate,Gate Oxide Thickness Scaling,Lift-off Techniques,Program Erase Speed Analysis[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Funding details” size=”size-sm” text_align=”text-left”][vc_column_text][/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”DOI” size=”size-sm” text_align=”text-left”][vc_column_text]https://doi.org/10.1109/ICEEI.2017.8312435[/vc_column_text][/vc_column_inner][vc_column_inner width=”1/4″][vc_column_text]Widget Plumx[/vc_column_text][/vc_column_inner][/vc_row_inner][/vc_column][/vc_row][vc_row][vc_column][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][/vc_column][/vc_row]