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Hardware Trojan Design and Its Detection using Side-Channel Analysis on Cryptographic Hardware AES Implemented on FPGA
Hanindhito B.a, Kurniawan Y.a
a School of Electrical Engineering and Informatics, Institut Teknologi Bandung, Department of Electrical Engineering, Bandung, Indonesia
[vc_row][vc_column][vc_row_inner][vc_column_inner][vc_separator css=”.vc_custom_1624529070653{padding-top: 30px !important;padding-bottom: 30px !important;}”][/vc_column_inner][/vc_row_inner][vc_row_inner layout=”boxed”][vc_column_inner width=”3/4″ css=”.vc_custom_1624695412187{border-right-width: 1px !important;border-right-color: #dddddd !important;border-right-style: solid !important;border-radius: 1px !important;}”][vc_empty_space][megatron_heading title=”Abstract” size=”size-sm” text_align=”text-left”][vc_column_text]© 2019 IEEE.Nowadays, an integrated circuit can carry many functions which make them more challenging to design and manufacture. The involvement of the third party is not unusual which can open the possibilities for unauthorized modification by inserting illegal block called hardware trojan to perform some malicious functions. This issue raises attention in the field of hardware security to prevent the insertion of the hardware trojan and to detect its presence in a chip. Side channel analysis is considered as a prospective method, although there are several difficulties encountered. In this paper, we will implement cryptographic hardware that can encrypt information using Advanced Encryption Standards (AES) in a Field Programmable Gate Arrays (FPGA). Then, this reference model is subjected to the implantation of hardware trojan designed to leak the AES key. By using the side channel analysis and by adjusting the behavior of the hardware trojan, we will try to detect its presence using conventional instruments available in our labs. In the end, we can conclude the possibility for the end customer to detect the existence of hardware trojan and the design techniques of hardware trojan to evade the detection.[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Author keywords” size=”size-sm” text_align=”text-left”][vc_column_text]Advanced Encryption Standard,Conventional instruments,Cryptographic hardware,Design and manufactures,Design technique,Reference modeling,Side-channel analysis,Unauthorized modification[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Indexed keywords” size=”size-sm” text_align=”text-left”][vc_column_text]Advanced Encryption Standard,cryptographic hardware,Field Programmable Gate Arrays,hardware trojan,integrated circuit,side channel analysis[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Funding details” size=”size-sm” text_align=”text-left”][vc_column_text][/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”DOI” size=”size-sm” text_align=”text-left”][vc_column_text]https://doi.org/10.1109/ICEEI47359.2019.8988803[/vc_column_text][/vc_column_inner][vc_column_inner width=”1/4″][vc_column_text]Widget Plumx[/vc_column_text][/vc_column_inner][/vc_row_inner][/vc_column][/vc_row][vc_row][vc_column][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][/vc_column][/vc_row]