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Transaction level modeling for early verification on embedded system design
Abdurohman M.a, Kuspriyantob, Sutikno S.b, Sasongko A.b
a Informatic Dept. IT Telkom, Indonesia
b STEI, Institut Teknologi Bandung, Indonesia
[vc_row][vc_column][vc_row_inner][vc_column_inner][vc_separator css=”.vc_custom_1624529070653{padding-top: 30px !important;padding-bottom: 30px !important;}”][/vc_column_inner][/vc_row_inner][vc_row_inner layout=”boxed”][vc_column_inner width=”3/4″ css=”.vc_custom_1624695412187{border-right-width: 1px !important;border-right-color: #dddddd !important;border-right-style: solid !important;border-radius: 1px !important;}”][vc_empty_space][megatron_heading title=”Abstract” size=”size-sm” text_align=”text-left”][vc_column_text]Time-to-market pressure and productivity gap are two factors that encourage the Electronic Design Automation (EDA) industry and researcher of embedded system to enhanche embedded system design method. Current embedded system desing approach, Register Transfer Level, is not sufficient to fullfil the embedded system design necessity. It needs a new design method above RTL, higher abstraction layer. Electronic System Level is general term that used to name system above RTL. ESL definition so far is a system above RTL including hardware and software. In this paper we designed a Transaction Level Modeling (TLM) for early verification on embedded system design. This modeling is used to know fungtionality fulfilment at early stage. We specify four kind model for early verification purpose. © 2009 IEEE.[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Author keywords” size=”size-sm” text_align=”text-left”][vc_column_text]Abstraction layer,Early verification),Electronic design automation,Electronic system level,Electronic System Level (ESL),Embedded system design,Hardware and software,New design,Register transfer level,Register Transfer level(RTL),Time-to-market,Transaction level modeling,Transaction Level Modeling(TLM)[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Indexed keywords” size=”size-sm” text_align=”text-left”][vc_column_text]Early verification),Electronic System Level (ESL),Register Transfer level(RTL),Transaction Level Modeling(TLM)[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Funding details” size=”size-sm” text_align=”text-left”][vc_column_text][/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”DOI” size=”size-sm” text_align=”text-left”][vc_column_text]https://doi.org/10.1109/ICIS.2009.41[/vc_column_text][/vc_column_inner][vc_column_inner width=”1/4″][vc_column_text]Widget Plumx[/vc_column_text][/vc_column_inner][/vc_row_inner][/vc_column][/vc_row][vc_row][vc_column][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][/vc_column][/vc_row]