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An architectural design of a multimedia over IP (MoIP) terminal
a Department of Electrical Engineering, IURC Microelectronics, Bandung Institute of Technology, West Java, 40132, Indonesia
[vc_row][vc_column][vc_row_inner][vc_column_inner][vc_separator css=”.vc_custom_1624529070653{padding-top: 30px !important;padding-bottom: 30px !important;}”][/vc_column_inner][/vc_row_inner][vc_row_inner layout=”boxed”][vc_column_inner width=”3/4″ css=”.vc_custom_1624695412187{border-right-width: 1px !important;border-right-color: #dddddd !important;border-right-style: solid !important;border-radius: 1px !important;}”][vc_empty_space][megatron_heading title=”Abstract” size=”size-sm” text_align=”text-left”][vc_column_text]© 2002 IEEE.This paper presents an architectural design of a low-cost multimedia over Internet protocol (MoIP) terminal based on H.323. The architectural design provides a way of studying low-cost MoIP terminal feasibility. Instead of designing an application specific chip, we decide to use a programmable digital signal processing (DSP) based approach. It consists of software and hardware designs on commercial off the shelf (COTS) components. The software module consists of media processing and control. The hardware part is based on the 150 MHz TMS320C6711 processor having a 900 MFLOPS capability. The preliminary design shows that real-time MoIP software needs approximately 500 MOPS because of video and audio processing needs as well as H.323 control protocol. It can be implemented in a 100 mm x 100 mm board size. The power consumption is as small as 6 watt. With this design, a terminal can cost less than $250 for a quantity as few as 1000 unit. Hence a low-cost MoIP is feasible using existing COTS components.[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Author keywords” size=”size-sm” text_align=”text-left”][vc_column_text]Application specific,Commercial off-the-shelf components,Control protocols,Digital signal processing (DSP),Digital signal processing chips,Preliminary design,Signal design,Software and hardwares[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Indexed keywords” size=”size-sm” text_align=”text-left”][vc_column_text]Application software,Costs,Digital signal processing chips,Energy consumption,Hardware,Internet,Process control,Protocols,Signal design,Software design[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Funding details” size=”size-sm” text_align=”text-left”][vc_column_text][/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”DOI” size=”size-sm” text_align=”text-left”][vc_column_text]https://doi.org/10.1109/APCCAS.2002.1114983[/vc_column_text][/vc_column_inner][vc_column_inner width=”1/4″][vc_column_text]Widget Plumx[/vc_column_text][/vc_column_inner][/vc_row_inner][/vc_column][/vc_row][vc_row][vc_column][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][/vc_column][/vc_row]