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Design of reconfigurable system-on-chip architecture for optical wireless communication
Fuada S.a, Adiono T.b, Putra A.P.b, Setiawan E.b
a Universitas Pendidikan Indonesia, Indonesia
b Institut Teknologi Bandung, Bandung, Indonesia
[vc_row][vc_column][vc_row_inner][vc_column_inner][vc_separator css=”.vc_custom_1624529070653{padding-top: 30px !important;padding-bottom: 30px !important;}”][/vc_column_inner][/vc_row_inner][vc_row_inner layout=”boxed”][vc_column_inner width=”3/4″ css=”.vc_custom_1624695412187{border-right-width: 1px !important;border-right-color: #dddddd !important;border-right-style: solid !important;border-radius: 1px !important;}”][vc_empty_space][megatron_heading title=”Abstract” size=”size-sm” text_align=”text-left”][vc_column_text]© 2019 Journal of Communications.To meet the growing demands of the data communication infrastructure in the Internet-of-Things era, alternative methods are needed to complement the current technology, one of which employs optics-based communication. In this paper, we develop optical wireless communication (OWC) infrastructure focuses on digital signal processing (DSP) part. We design System-on-Chip (SoC) architecture based on the Orthogonal Frequency-Division Multiplexing (OFDM) technique with reconfigurable hardware resources. The system developed combines ARM microprocessors with FPGAs. For accelerating the digital processing, several essential parts such as Viterbi decoder, FFT, and time synchronizer are applied to the hardware IP (H/W SoC). While the scheduling is carried out on the software (S/W SoC). With this system, the data communication with other devices can be practiced easily, using various peripherals, i.e., Ethernet, UART, and serial-based connection. Afterward, we exploit the system performance in terms of the hardware resources utilization both for DSP Transmitter and DSP Receiver, also the system latency.[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Author keywords” size=”size-sm” text_align=”text-left”][vc_column_text][/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Indexed keywords” size=”size-sm” text_align=”text-left”][vc_column_text]Digital Signal Processing (DSP),OFDM,Optical Wireless Communication (OWC),System-on-Chip (SoC)[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Funding details” size=”size-sm” text_align=”text-left”][vc_column_text][{‘$’: ‘This work was supported by the Royal Academy of Engineering (RAENG), United Kingdom, through Industry-Academia Partnership Programme under Grant No. IAPP1\\100074 collaborated with University of Edinburgh, UK.’}, {‘$’: ‘Manuscript received March 15, 2019; revised September 5, 2019. This work was supported by the Royal Academy of Engineering (RAENG), United Kingdom, through Industry-Academia Partnership Programme under Grant No. IAPP1\\100074 collaborated with University of Edinburgh, UK. Corresponding author email: syifaulfuada@upi.edu doi:10.12720/jcm.14.10.965-970’}][/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”DOI” size=”size-sm” text_align=”text-left”][vc_column_text]https://doi.org/10.12720/jcm.14.10.965-970[/vc_column_text][/vc_column_inner][vc_column_inner width=”1/4″][vc_column_text]Widget Plumx[/vc_column_text][/vc_column_inner][/vc_row_inner][/vc_column][/vc_row][vc_row][vc_column][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][/vc_column][/vc_row]