[vc_empty_space][vc_empty_space]
A configurable and low complexity hard-decision viterbi decoder in VLSI architecture
Putra R.V.W.a, Adiono T.a
a Microelectronics Center, Institut Teknologi Bandung, Bandung, Indonesia
[vc_row][vc_column][vc_row_inner][vc_column_inner][vc_separator css=”.vc_custom_1624529070653{padding-top: 30px !important;padding-bottom: 30px !important;}”][/vc_column_inner][/vc_row_inner][vc_row_inner layout=”boxed”][vc_column_inner width=”3/4″ css=”.vc_custom_1624695412187{border-right-width: 1px !important;border-right-color: #dddddd !important;border-right-style: solid !important;border-radius: 1px !important;}”][vc_empty_space][megatron_heading title=”Abstract” size=”size-sm” text_align=”text-left”][vc_column_text]© 2014 IEEE.Convolutional encoding and viterbi algorithm are basic concepts of error correction method. Specifically, viterbi algorithm is one of decoding method for data error correction. This algorithm is used widely in many communication applications. Hence, many researches have been conducted to achieve an efficient implementation of this algorithm. In VLSI area, the design challenges are usually about its power, area consumption, speed, complexity, and configurability. This paper proposed a configurable and low complexity design for hard-decision viterbi decoder in VLSI. The design can be configured for any number of traceback by increasing or decreasing the size of traceback parameters. It needs N+2 clock cycles latency to complete the process, which N is the number of traceback. In this research, configuration test have been conducted for N=32 and N=64. The design also has been synthesized in both FPGA Altera and Xilinx as target boards. It gives good synthesis results in operational speed and area consumption.[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Author keywords” size=”size-sm” text_align=”text-left”][vc_column_text]Communication application,configurable,Convolutional encoding,Efficient implementation,low complexity,Viterbi decoder,VLSI,VLSI architectures[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Indexed keywords” size=”size-sm” text_align=”text-left”][vc_column_text]configurable,low complexity,viterbi decoder,VLSI[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Funding details” size=”size-sm” text_align=”text-left”][vc_column_text][/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”DOI” size=”size-sm” text_align=”text-left”][vc_column_text]https://doi.org/10.1109/ICoICT.2014.6914062[/vc_column_text][/vc_column_inner][vc_column_inner width=”1/4″][vc_column_text]Widget Plumx[/vc_column_text][/vc_column_inner][/vc_row_inner][/vc_column][/vc_row][vc_row][vc_column][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][/vc_column][/vc_row]