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The efficient mCBE algorithm and quantization numbers for multiplierless and low complexity DCT/IDCT Image Compression Architecture
Wicaksana Putra R.V.a, Mareta R.a, Anbarsanti N.a, Adiono T.a
a Electrical Engineering, Bandung Institute of Technology, Indonesia
[vc_row][vc_column][vc_row_inner][vc_column_inner][vc_separator css=”.vc_custom_1624529070653{padding-top: 30px !important;padding-bottom: 30px !important;}”][/vc_column_inner][/vc_row_inner][vc_row_inner layout=”boxed”][vc_column_inner width=”3/4″ css=”.vc_custom_1624695412187{border-right-width: 1px !important;border-right-color: #dddddd !important;border-right-style: solid !important;border-radius: 1px !important;}”][vc_empty_space][megatron_heading title=”Abstract” size=”size-sm” text_align=”text-left”][vc_column_text]This paper presents a multiplierless and low complexity of DCT/IDCT Image Compression Architecture by using two approaches. First, we propose multiplication decomposition by using our algorithm. This algorithm minimizes shifter-adder components to substitute multiplier efficiently. We named it as multiplication from Common Binary Expression (mCBE) Algorithm. Second, we propose alternative quantization numbers which can be simply implemented as shifter in digital hardware. These numbers can also retain good quality of compressed image compared to JPEG recommendation numbers. We named them as FathQuantz Numbers. Those improvements lead our proposed architecture becomes multiplierless and low complexity. The result states that our proposed 8-points 1D-DCT design has only 6 stages and 8-points 1D-IDCT design has only 7 stages. Here, we define 1 stage is equal to shifter or 2-inputs adder delay. So, by pipelining method, we can achieve high speed architecture with latency as trade off consideration. This design has been synthesized and it can speed up to 1.41ns crithical path delay (709.22MHz). © 2011 IEEE.[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Author keywords” size=”size-sm” text_align=”text-left”][vc_column_text]DCT/IDCT architectures,FathQuantz Numbers,Low complexity,mCBE Algorithm,Multiplierless[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Indexed keywords” size=”size-sm” text_align=”text-left”][vc_column_text]DCT/IDCT architecture,FathQuantz Numbers,low complexity,mCBE Algorithm,multiplierless[/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”Funding details” size=”size-sm” text_align=”text-left”][vc_column_text][/vc_column_text][vc_empty_space][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][vc_empty_space][megatron_heading title=”DOI” size=”size-sm” text_align=”text-left”][vc_column_text]https://doi.org/10.1109/ICEEI.2011.6021774[/vc_column_text][/vc_column_inner][vc_column_inner width=”1/4″][vc_column_text]Widget Plumx[/vc_column_text][/vc_column_inner][/vc_row_inner][/vc_column][/vc_row][vc_row][vc_column][vc_separator css=”.vc_custom_1624528584150{padding-top: 25px !important;padding-bottom: 25px !important;}”][/vc_column][/vc_row]